Logical physical layer interface specification support for PCie 6.0, cxl 3.0, and UPI 3.0 protocols
AssigneeIntel Corporation
InventorsSwadesh Choudhary, Mahesh Wagh, Debendra Das Sharma
Life of this patent
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Abstract
In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.
Claims19
An apparatus comprising:
- a first link layer circuit to perform link layer functionality for a first communication protocol;
- a second link layer circuit to perform link layer functionality for a second communication protocol;
- a selection circuit coupled to the first link layer circuit via a first logical PHY interface (LPIF) link and coupled to the second link layer circuit via a second LPIF link, to provide first information from the first link layer circuit to a logical physical (logPHY) circuit and second information from the second link layer circuit to the logPHY circuit;
- and
- the logPHY circuit coupled to the selection circuit via a third LPIF link, wherein the logPHY circuit is to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and communicate with the second link layer circuit in a non-flit mode in which the second information is communicated in a variable width size,
- wherein the first link layer circuit is to start a flit header in a middle of a flit and send the flit with the flit header to the logPHY circuit.
At least one non-transitory computer readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving, in a logical physical (logPHY) circuit, a flit;
- sending, from the logPHY circuit, the flit to a link layer circuit coupled to the logPHY circuit in parallel with checking, in the logPHY circuit, the flit for an error;
- detecting, in the logPHY circuit, the error in the flit;
- and
- sending a flit cancel signal to the link layer circuit to cause the link layer circuit to drop the flit.
An apparatus comprising:
- a first link layer circuit to perform link layer functionality for a first communication protocol;
- a second link layer circuit to perform link layer functionality for a second communication protocol;
- a selection circuit coupled to the first link layer circuit and the second link layer circuit, to provide first information from the first link layer circuit to a logical physical (logPHY) circuit and second information from the second link layer circuit to the logPHY circuit;
- and
- the logPHY circuit coupled to the selection circuit, wherein the logPHY circuit is to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and communicate with the second link layer circuit in a non-flit mode in which the second information is communicated in a variable width size,
- wherein when a link is in a partial width mode, the logPHY circuit is to send an early valid indication to the first link layer circuit to enable the first link layer circuit to power up ahead of receipt of a flit from the logPHY circuit.
Dependencies are inferred from the claim text.