A memory module operable in a computer system, the computer system including a memory controller, at least one module slot, and a memory bus between the memory controller and the at least one module slot, the memory bus including address and control signal lines, data signal lines and data strobe signal lines, the memory module comprising:
- a printed circuit board having a plurality of edge connections configured to be electrically coupled to a corresponding plurality of contacts of a module slot of the computer system to provide electrical connections between the memory bus and components of the memory module mounted on the printed circuit board;
- memory devices mounted on the printed circuit board, the memory devices including at least first memory devices and second memory devices, wherein the first memory devices form a first rank and the second memory devices form a second rank;
- logic coupled to the printed circuit board, wherein the logic is configurable to receive, via the control signal lines and address signal lines, first input control signals and first input address signals associated with a first memory read command for reading first data from memory devices in the first rank, and second input control signals and second input address signals associated with a second memory read command for reading second data from memory devices in the second rank, and to output first registered control signals and first registered address signals corresponding to the first memory read command, and second registered control signals and second registered address signals corresponding to the second memory read command;
- circuitry coupled between the memory devices and the data signal lines and data strobe signal lines in the memory bus, wherein the circuitry is coupled to at least one memory device in the first rank via a first set of module data and strobe signal lines, to at least one memory device in the second rank via a second set of module data and strobe signal lines, and to at least a subset of the data signal lines and at least a subset of the data strobe signal lines;
- the at least one memory device in the first rank in response to the first registered control signals and first registered address signals is selected to output a first set of data and data strobe signals onto the first set of module data and data strobe signal lines, the first set of data and data strobe signals including a first data signal and a first data strobe signal, the first data signal including a first number of data bits, the first data strobe signal including a first preamble, a first post-amble, and a first number of consecutive data strobe edges between the first preamble and the first post-amble, the first number of consecutive data strobe edges respectively corresponding to the first number of data bits;
- the at least one memory device in the second rank in response to the second registered control signals and second registered address signals is selected to output a second set of data and data strobe signals unto a second set of module data and data strobe signal lines, the second set of data and strobe signals including a second data signal and a second data strobe signal, the second data signal including a second number of data bits, the second data strobe signal including a second preamble, a second post-amble, and a second number of consecutive data strobe edges between the second preamble and the second post-amble, the second number of consecutive data strobe edges respectively corresponding to the second number of data bits, the first data strobe signal at least partially preceding the second data strobe signal in time;
- and
- the circuitry is further configurable to
- receive the first set of data and data strobe signals via the first set of module data and strobe signal lines;
- receive the second set of data and data strobe signals via the second set of data and strobe signal lines;
- output a combined data signal including a third number of data bits onto a corresponding data signal line of the subset of the data signal lines, the third number of data bits including the first number of data bits and the second number of data bits;
- and
- output a combined data strobe signal unto a corresponding data strobe signal line of the subset of the data strobe signal lines, the combined data strobe signal including a third preamble, a third post-amble, and a third number of consecutive data strobe edges between the third preamble and the third post-amble, the third number of consecutive data strobe edges including data strobe edges respectively corresponding to the third number of data bits.