Insertion/promotion vectors to update replacement data in caches based on criticality
AssigneeApple Inc.
InventorsTyler J. Huberty, Henry A. Pellerin, Daniel A. Jimenez
Life of this patent
Estimating the term…
Abstract
A cache memory supports a plurality of insertion/promotion vectors (IPVs) and a replacement control circuit configured to update replacement data for the cache memory based on the plurality of IPVs. In one embodiment, the IPV is selected for a given request based a criticality status of a cache line accessed by the given request. For example, cache lines deemed important or critical for performance reasons may be replaced less frequently via a first IPV, while non-critical cache lines are replaced more frequently via a second IPV.
Claims20
An apparatus comprising:
- a cache memory configured to store a plurality of cache lines;
- a plurality of clocked storage devices configured to store a plurality of insertion and promotion vectors (IPVs);
- and
- a replacement control circuit coupled to the cache memory and to the plurality of clocked storage devices, wherein:
- the replacement control circuit is configured to maintain replacement data corresponding to the cache memory based on the plurality of IPVs, and
- the replacement control circuit is configured to select a selected IPV of the plurality of IPVs to update the replacement data for a given access request to the cache memory based on a criticality level of a particular cache line accessed by the given access request.
A method comprising:
- storing, by a computing device, a plurality of cache lines for a cache memory and a plurality of insertion and promotion vectors (IPVs) for the cache memory;
- maintaining, by the computing device using the plurality of the IPVs, replacement data for the cache memory;
- receiving, by the computing device, an access request to the cache memory;
- determining, by the computing device, a criticality level of a particular cache line corresponding to the access request;
- selecting, by the computing device based on the criticality level of the particular cache line, a selected IPV of the plurality of IPVs;
- and
- updating, by the computing device using the selected IPV, the replacement data for the access request.
A non-transitory computer readable storage medium having instructions of a hardware description language stored thereon, wherein the instructions are executable by a computing system to program the computing system to generate a computer simulation model, wherein the computer simulation model represents a hardware circuit that includes:
- a cache memory configured to store a plurality of cache lines;
- a plurality of clocked storage devices configured to store a plurality of insertion and promotion vectors (IPVs);
- and
- a replacement control circuit coupled to the cache memory and to the plurality of clocked storage devices, wherein:
- the replacement control circuit is configured to maintain replacement data corresponding to the cache memory based on the plurality of IPVs, and
- the replacement control circuit is configured to select a selected IPV of the plurality of IPVs to update the replacement data for a given access request to the cache memory based on a criticality level of a particular cache line accessed by the given access request.
Dependencies are inferred from the claim text.