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US 12,222,873 B2Granted
Method and apparatus to enable a cache (DEVPIC) to store process specific information inside devices that support address translation service (ATS)
AssigneeIntel Corporation
InventorsRupin Vakharwala, Vedvyas Shanbhogue
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Abstract
Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to PCIe Address Translation Service (ATS) to allow devices to have a DevTLB that caches address translation (per page) information in conjunction with a Device ProcessInfoCache (DevPIC) that will store process specific information. Other embodiments may be described and/or claimed.
Claims19
An apparatus comprising:
- a cache memory having a plurality of entries, each of the plurality of entries to store process specific information for a process;
- a device translation lookaside buffer (DevTLB) having a plurality of entries each to store a virtual address-to-physical address translation received from an input/output memory management unit (IOMMU);
- and
- at least one processor coupled to the cache memory and the DevTLB, wherein the apparatus comprises a Peripheral Component Interconnect Express (PCIe) device to couple with at least one central processing unit (CPU) and a shared virtual memory (SVM), to communicate, to the CPU, capability information to indicate that the PCIe device includes the cache memory to store the process specific information, and enable the cache memory in response to a configuration message from the CPU.
1 more element
A method comprising:
- communicating, from a Peripheral Component Interconnect Express (PCIe) device to a processor, capability information of the PCIe device, the capability information to indicate that the PCIe device includes a process information cache to store process specific information;
- receiving a configuration message from the processor and enabling the process information cache, in response to the configuration message;
- receiving first process specific information from an input/output memory management unit (IOMMU);
- and
- storing the first process specific information in a first entry of the process information cache in association with a process address space identifier (PASID).
2 more elements
A system comprising:
- at least one central processing unit (CPU), the at least one CPU to send an offload request to at least one accelerator, the at least one CPU comprising:
- a memory management unit (MMU) to translate a linear address to a physical address;
- and
- mask circuitry to mask one or more portions of a linear address and provide the masked linear address to the MMU;
- the at least one accelerator coupled to the CPU, the at least one accelerator to perform an operation in response to the offload request, the at least one accelerator comprising:
- a cache memory having a plurality of entries, each of the plurality of entries to store process specific information for a process;
- an input/output MMU (IOMMU) coupled between the at least one CPU and the at least one accelerator;
- and
- a memory coupled to the at least one CPU and the at least one accelerator, the at least one CPU and the at least one accelerator to interact with the memory according to a shared virtual memory (SVM) model,
- wherein:
- the at least one CPU is to send the offload request to the at least one accelerator, the offload request comprising an unmasked linear address, the unmasked linear address including metadata of a process;
- and
- the at least one accelerator is to communicate, to the at least one CPU, capability information to indicate that the at least one accelerator includes the cache memory to store the process specific information, and enable the cache memory in response to a configuration message from the at least one CPU.
10 more elements
Dependencies are inferred from the claim text.