Methods and apparatuses for addressing memory caches

A cache memory, comprising:

• cache lines on a die in a semiconductor package to store information within the semiconductor package, the stored information within the semiconductor package being associated with physical addresses comprising at least first and second non-overlapping, distinct predefined portions, the cache lines being indexed by the second portions of respective physical addresses associated with the stored information;
• one or more tables, each table comprising respective table entries indexed by the first portions of the respective physical addresses, wherein the respective table entries in each of the one or more tables store indications of the second portions of respective physical addresses associated with the stored information;
• first circuitry coupled to at least one of the one or more tables to determine whether the second portion of a specified physical address matches the indication, of the second portion of a respective physical address, stored in a table entry identified by the first portion of the specified physical address;
• second circuitry coupled to the cache lines and the first circuitry, to forward information from a cache line identified by the second portion of the specified physical address in accordance with a cache hit signal;
• and
• the die, configured to be connected to a processor die by through-silicon vias.