Memory access control through permissions specified in page table entries for execution domains
AssigneeMicron Technology, Inc.
InventorSteven Jeffrey Wallach
Life of this patent
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Abstract
Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.
Claims20
A device, comprising:
- a page table having a plurality of page table entries, including a first page table entry configured to specify:
- a base to map a virtual memory address region to a physical memory address region;
- and
- a list of permissions for a plurality of domains of routines respectively;
- and
- a logic circuit configured to, in response to an instruction of a routine executed in a processor to access a virtual memory address in a virtual memory address region:
- determine, based on the list of permissions, a permission to access, by execution of the instruction in a routine having a first domain among the plurality of domains, the physical memory address region;
- and
- control, based on the permission, the execution of the instruction in accessing, via the virtual memory address, the physical memory address region.
A method, comprising:
- specifying, in a first page table entry in a page table having a plurality of page table entries;
- a base to map a virtual memory address region to a physical memory address region;
- and
- a list of permissions for a plurality of domains of routines respectively;
- and
- in response to an instruction of a routine executed in a processor to access a virtual memory address in the virtual memory address region:
- determining, by a logic circuit and based on the list of permissions, a permission to access, by execution of the instruction in a routine having a first domain among the plurality of domains, the physical memory address region;
- and
- controlling, by the logic circuit and based on the permission, the execution of the instruction in accessing, via the virtual memory address, the physical memory address region.
An apparatus, comprising:
- a memory configured to store a plurality of routines classified in a plurality of domains;
- a processor coupled with the memory;
- and
- a memory management unit, comprising:
- a page table having a plurality of page table entries, including a first page table entry configured to specify:
- a base to map a virtual memory address region to a physical memory address region in the memory;
- and
- a list of permissions for the plurality of domains respectively;
- and
- a logic circuit configured to, in response to an instruction of a routine executed in a processor to access a virtual memory address in the virtual memory address region:
- determine, based on the list of permissions, a permission to access, by execution of the instruction in a routine having a first domain among the plurality of domains, the physical memory address region;
- and
- control, based on the permission, the execution of the instruction in accessing, via the virtual memory address, the physical memory address region.
Dependencies are inferred from the claim text.