Processor, computer system, and method for flushing hierarchical cache structure based on a designated key identification code and a designated address

A processor, flushing a hierarchical cache structure based on a designated key identification code and a designated address, comprising:

• a first core, including a decoder, a memory ordering buffer, and a first in-core cache module;
• and
• a last-level cache;
• wherein:
• in response to an instruction of an instruction set architecture that is provided to flush the hierarchical cache structure based on the designated key identification code and the designated address, the decoder outputs at least one microinstruction;
• according to the at least one microinstruction, a flushing request with the designated key identification code and the designated address is provided to the first in-core cache module through the memory ordering buffer, and then is provided to the last-level cache by the first in-core cache module;
• in response to the flushing request, the last-level cache searches itself the last-level cache for a matching cache line that matches the designated key identification code and the designated address, and flushes the matching cache line.

A method for flushing a hierarchical cache structure based on a designated key identification code and a designated address, comprising:

• in response to an instruction of an instruction set architecture that is provided to flush the hierarchical cache structure based on the designated key identification code and the designated address, operating a decoder to output at least one microinstruction, wherein the decoder is provided by a first core of a first processor on a first die, and the first core further comprises a memory ordering buffer and a first in-core cache module;
• and
• according to the at least one microinstruction, providing a flushing request that carries the designated key identification code and the designated address to the first in-core cache module through the memory ordering buffer, and then operating the first in-core cache module to provide the flushing request to a first last-level cache shared by a plurality of cores of the first processor;
• and
• in response to the flushing request, operating the first last-level cache to search itself the first last-level cache for a matching cache line that matches the designated key identification code and the designated address, and flush the matching cache line.