Encoding and decoding method, apparatus and device based on erasure pool, and storage medium

An encoding and decoding device based on an erasure pool, comprising:

• a memory, configured to store a computer program;
• and
• one or more processors,
• herein, when the computer program is executed by the one or more processors, the one or more processors are enabled to:
• store, upon receiving original data that needs to be subjected to data encoding and decoding, the original data into a shared memory;
• send an encoding and decoding signal to an encoding and decoding process, so that the encoding and decoding process obtains the original data from the shared memory after receiving the encoding and decoding signal, and calls a hard codec plug-in to perform a hard encoding and decoding operation;
• control, in a case that a failure or hot plugging occurs to the accelerator chip, which will lead to a failure of the encoding and decoding operation, the encoding and decoding process to call a soft codec plug-in to perform a soft encoding and decoding operation;
• and
• obtain, after the encoding and decoding process completes the encoding and decoding operation, an encoding and decoding result from the shared memory,
• wherein the encoding and decoding process obtains the original data from the shared memory after receiving the encoding and decoding signal, and calls the hard codec plug-in to perform the hard encoding and decoding operation specifically comprises:
• the encoding and decoding process obtains the original data from the shared memory after receiving the encoding and decoding signal;
• and
• the encoding and decoding process calls a driver API of an accelerator chip by calling a hard codec plug-in interface, and calls a corresponding encoding and decoding function to perform the hard encoding and decoding operation by utilizing the accelerator chip.

A computer readable storage medium, wherein the computer readable storage medium stores a computer program therein, when the computer program is executed by one or more processors, the one or more processors are enabled to:

• store, upon receiving original data that needs to be subjected to data encoding and decoding, the original data into a shared memory;
• send an encoding and decoding signal to an encoding and decoding process, so that the encoding and decoding process obtains the original data from the shared memory after receiving the encoding and decoding signal, and calls a hard codec plug-in to perform a hard encoding and decoding operation;
• control, in a case that a failure or hot plugging occurs to the accelerator chip, which will lead to a failure of the encoding and decoding operation, the encoding and decoding process to call a soft codec plug-in to perform a soft encoding and decoding operation;
• and
• obtain, after the encoding and decoding process completes the encoding and decoding operation, an encoding and decoding result from the shared memory,
• wherein the encoding and decoding process obtains the original data from the shared memory after receiving the encoding and decoding signal, and calls the hard codec plug-in to perform the hard encoding and decoding operation specifically comprises:
• the encoding and decoding process obtains the original data from the shared memory after receiving the encoding and decoding signal;
• and
• the encoding and decoding process calls a driver API of an accelerator chip by calling a hard codec plug-in interface, and calls a corresponding encoding and decoding function to perform the hard encoding and decoding operation by utilizing the accelerator chip.