Systems and methods for optimizing battery life in information handling systems using intelligence implemented in storage systems

An information handling system, comprising:

• a solid state drive (SSD);
• a battery system comprising one or more internal battery cells;
• power-consuming circuitry that comprises at least one first programmable integrated circuit coupled to the SSD by a peripheral component interconnect express (PCIe) link, the power-consuming circuitry being coupled to selectably receive power from an external power source or from the one or more internal battery cells of the battery system;
• and
• at least one second programmable integrated circuit programmed to determine if a current value of a remaining battery capacity of the battery cells is less than or equal to a predefined low battery capacity threshold value while the power-consuming circuitry is currently receiving power only from the internal battery cells of the battery system, and then:
• operate the SSD in a low battery SSD power mode if the current value of the remaining battery capacity of the battery cells is determined to be less than or equal to the predefined low battery capacity threshold value while the external power source is not providing external power to the power-consuming circuitry of the information handling system, and
• operate the SSD in a default SSD power mode if the current value of the remaining battery capacity of the battery cells is determined to be greater than the predefined low battery capacity threshold value or if the external power source is providing external power to the power-consuming circuitry of the information handling system;
• and
• where the low battery SSD power mode comprises first peripheral component interconnect express (PCIe) link power management settings and first non-volatile memory express (NVMe) power settings, and where the at least one second programmable integrated circuit is programmed to operate the SSD in the low battery SSD power mode using the first peripheral component interconnect express (PCIe) link power management settings and the first non-volatile memory express (NVMe) power settings;
• where the default SSD power mode comprises different and second peripheral component interconnect express (PCIe) link power management settings and second non-volatile memory express (NVMe) power settings, and where the at least one second programmable integrated circuit is programmed to operate the SSD in the default SSD power mode using the second peripheral component interconnect express (PCIe) link power management settings and the second non-volatile memory express (NVMe) power settings;
• and
• where the power-consuming circuitry consumes greater power when the SSD operates in the default SSD power mode than when the SSD operates in the low battery SSD power mode;
• where the first NVMe power settings comprise a first value of Idle Time Prior to Transit (ITPT) that is less than a second value of ITPT of the second NVMe power settings.