Timestamp alignment across multiple computing nodes
AssigneeIntel Corporation
InventorsMark Bordogna, Jonathan A. Robinson
Life of this patent
Estimating the term…
Abstract
Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.
Claims21
An apparatus comprising:
- a network interface device comprising:
- a first interface to a first processor and
- circuitry to receive a time stamp from the first processor by the first interface, wherein:
- receipt of the time stamp from the first processor by the first interface is to cause the circuitry to provide, to the first processor, a time stamp value based on a clock signal from a clock source corresponding to the received time stamp from the first processor and
- the first processor is to adjust a time stamp counter value based, at least in part, on the time stamp value based on the clock signal corresponding to the received time stamp from the first processor.
A method comprising:
- a first processor node providing first and second time stamp counter (TSC) values to a network interface device to cause the network interface device to provide a first TSC value-primary timer value pair to the first processor node and provide a second TSC value-primary timer value pair to the first processor node;
- the first processor node determining a first offset of the first TSC for the first processor node relative to the primary timer based on the first and second TSC value-primary timer value pairs received from the network interface device;
- and
- the first processor node adjusting values of the TSC for the first processor node based on the first offset.
An apparatus comprising:
- a first processor node comprising a first processor and a first time stamp counter (TSC) source, wherein:
- by a copy of a first value of the first TSC source to a network interface device, the first processor node is to initiate and cause the network interface device to transfer a primary time stamp value recorded for the first value of the first TSC source from the network interface device to the first processor node.
Dependencies are inferred from the claim text.