Methods and apparatus to facilitate safe startup of a power management unit

An integrated circuit comprising:

• first voltage measurement circuitry including an input terminal and an output terminal;
• second voltage measurement circuitry including:
• delay circuitry including an input terminal and an output terminal, the input terminal coupled to the output terminal of the first voltage measurement circuitry;
• a logic gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic gate coupled to the output terminal of the first voltage measurement circuitry, the second input terminal coupled to the output terminal of the delay circuitry;
• and
• a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal, and the output terminal of the comparator coupled to the third input terminal of the logic gate;
• a regulator including an input terminal and an output terminal, the input terminal of the regulator coupled to the output terminal of the logic gate;
• and
• a clock generator including an input terminal coupled to the output terminal of the regulator.

An apparatus comprising:

• an input terminal;
• an output terminal;
• a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal;
• a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal;
• and
• a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal.