Array substrate, display panel, and display apparatus

A display panel, comprising:

• an array substrate;
• and
• a color film substrate, cell-assembled with the array substrate,
• wherein the array substrate comprises:
• a base substrate, comprising a display region and a peripheral region surrounding the display region;
• a plurality of clock lines, disposed on the base substrate and in the peripheral region, wherein the clock lines extend in a first direction;
• a plurality of clock leads, disposed on the base substrate and in the peripheral region, wherein the clock leads extend in a second direction, the first direction being intersected with the second direction;
• a plurality of shift register units, disposed on the base substrate and in the peripheral region, wherein the shift register units are connected to the clock lines by the clock leads;
• and
• a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate,
• wherein the clock lead further comprises a second clock lead, wherein the compensation capacitor plate connected to the second clock lead comprises a first segment and a second segment that are connected sequentially in the first direction, a width of the first segment and a width of the second segment being different in the second direction, and a length of the second clock lead being less than a length of the first clock lead.

A display apparatus, comprising a display panel which comprises:

• an array substrate;
• and
• a color film substrate, cell-assembled with the array substrate,
• wherein the array substrate comprises:
• a base substrate, comprising a display region and a peripheral region surrounding the display region;
• a plurality of clock lines, disposed on the base substrate and in the peripheral region, wherein the clock lines extend in a first direction;
• a plurality of clock leads, disposed on the base substrate and in the peripheral region, wherein the clock leads extend in a second direction, the first direction being intersected with the second direction;
• a plurality of shift register units, disposed on the base substrate and in the peripheral region, wherein the shift register units are connected to the clock lines by the clock leads;
• and
• a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate,
• wherein the clock lead further comprises a second clock lead, wherein the compensation capacitor plate connected to the second clock lead comprises a first segment and a second segment that are connected sequentially in the first direction, a width of the first segment and a width of the second segment being different in the second direction, and a length of the second clock lead being less than a length of the first clock lead.