Fault tolerant synchronizer
AssigneeTexas Instruments Incorporated
InventorsDenis Roland Beaudoin, Samuel Paul Visalli
Life of this patent
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Abstract
A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.
Claims18
A synchronization circuit, comprising:
- a first synchronizer having a first data input, a first clock input, and first output;
- a second synchronizer having a second data input, a second clock input, and a second output;
- selection circuitry having first, second, and third inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively;
- the selection circuitry further including storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to an internal input of the selection circuitry.
A circuit, comprising:
- source circuitry;
- first flip-flop circuitry having a first input and a first output, the first input coupled to the source circuitry;
- destination circuitry;
- second flip-flop circuitry having a second input and a second output, the second input coupled to the destination circuitry;
- and
- synchronization circuitry having third and fourth inputs and third and fourth outputs, the third input coupled to the first output, the fourth input coupled to the second output, the third output coupled to the destination circuitry, and the fourth output coupled to the source circuitry.
Dependencies are inferred from the claim text.