Test board for testing memory signal

Abstract

A test board for testing a memory signal includes a first surface and a second surface. The first surface of the test board comprises a raised region and a non-raised region. The raised region is provided with a first connection area connectable to a main board, and a level at which the raised is located is higher than a level at which the non raised region is located by a preset value. The second surface of the test board includes a test area and a second connection area connectable to a memory chip. The test board is provided with a first connection harness for connecting the test area to the first connection area and a second connection harness for connecting the test area to the second connection area, to enable the memory signal of the memory chip to be tested based on the test area.

Dependencies are inferred from the claim text.