Testing method and testing system

A testing system, comprising

• a wafer under test, a detection machine and a processing device;
• the detection machine is configured to detect the wafer under test based on a pre-set test region, obtain detection results of a plurality of chips in the wafer under test, and upload the detection results to the processing device;
• the processing device is configured to obtain a discrete point distribution diagram of the detection results of the plurality of chips in the wafer under test, a discrete point in the discrete point distribution diagram being used for representing a position of an abnormal chip in the wafer under test;
• and
• the processing device is further configured to divide the discrete point distribution diagram into a plurality of test regions based on graphic distribution characteristics in the pre-set test region, obtain a test result distribution diagram, the test result distribution diagram being used for representing graphic characteristics of the discrete point distribution diagram, and obtain a correlation between the test result distribution diagram and the graphic distribution characteristics in the pre-set test region, and obtain a test result of the wafer under test based on the correlation;
• wherein the processing device is further configured to:
• receive the detection results;
• obtain the discrete point distribution diagram of the detection results of the plurality of chips in the wafer under test;
• divide the discrete point distribution diagram into the plurality of test regions based on the graphic distribution characteristics in the pre-set test region, and obtain the test result distribution diagram;
• obtain a correlation between the test result distribution diagram and the graphic distribution characteristics in the pre-set test region;
• and
• obtain a test result of the wafer under test based on the correlation;
• wherein
• when the detection results are of a category type, the detection results indicate that the plurality of chips under test in the wafer under test are normal chips or abnormal chips;
• and the processing device is configured to obtain a distribution diagram of positions of the abnormal chips in the wafer under test;
• or
• when the detection results are of a data type, the detection results indicate specific test numerical values of the plurality of chips under test in the wafer under test;
• and the processing device is configured to, for each of the chips under test in the wafer under test, obtain all the specific test numerical values corresponding to the chip under test, and judge whether the chip under test is a normal chip or an abnormal chip based on the specific test numerical values;
• and obtain the distribution diagram of the positions of the abnormal chips in the wafer under test;
• wherein the processing device is further configured to:
• arrange all the specific test numerical values in an ascending order according to sizes of the specific test numerical values;
• take any two detection results as a first detection result and a second detection result respectively from the ascending order arrangement, wherein the second detection result is greater than the first detection result;
• and
• when a specific test numerical value Q of all the specific test numerical values satisfies that:
• Q≤Q1−1.5*Igr or Q≥Q2+1.5*Iqr, take the specific test numerical value Q to be an abnormal test numerical value, wherein Q1 is a specific test numerical value of the first detection result, Q2is a specific test numerical value of the second detection result, and Iqr is a quartile deviation of the second detection result and the first detection result, and wherein the detection results corresponding to the chip under test at least including a pre-set number of abnormal test numerical values is taken as the discrete point.

A testing method, comprising:

• detecting a wafer under test based on a pre-set test region, to obtain detection results of a plurality of chips in the wafer under test;
• obtaining a discrete point distribution diagram of the detection results of the plurality of chips in the wafer under test, a discrete point in the discrete point distribution diagram being used for representing a position of an abnormal chip in the wafer under test;
• dividing the discrete point distribution diagram into a plurality of test regions based on graphic distribution characteristics in the pre-set test region, and obtaining a test result distribution diagram, the test result distribution diagram being used for representing graphic characteristics of the discrete point distribution diagram;
• obtaining a correlation between the test result distribution diagram and the graphic distribution characteristics in the pre-set test region;
• and
• obtaining a test result of the wafer under test based on the correlation;
• wherein said dividing the discrete point distribution diagram into the plurality of test regions based on the graphic distribution characteristics in the pre-set test region and obtaining the test result distribution diagram comprises:
• uniformly dividing the discrete point distribution diagram into a first test region, a second test region, a third test region and a fourth test region based on a concentric ring region division manner;
• and
• determining numbers and position differences of the discrete points in the first test region, the second test region, the third test region and the fourth test region, to obtain the test result distribution diagram.