Peak voltage detection circuit with reduced charge loss

A circuit structure comprising:

• a peak voltage detector coupling a first input node and a second input node to an output node, wherein the peak voltage detector includes,
• a first operational transconductance amplifier coupling the first input node and the second input node to an amplifier output node,
• a first transistor having a gate terminal coupled to the amplifier output node, and source/drain terminals coupling the amplifier output node to a supply voltage, and
• a second transistor having a gate terminal coupled to the amplifier output node, and source/drain terminals coupling the supply voltage to the output node of the peak voltage detector;
• an input line coupled to the first input node of the peak voltage detector;
• a first electrically actuated switch coupled to the second input node of the peak voltage detector;
• and
• a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor,
• wherein the first electrically actuated switch and the second electrically actuated switch each include a respective control node coupled to the input line, such that a signal in the input line enables current flow through the first electrically actuated switch and the second electrically actuated switch.

A circuit structure comprising:

• a peak voltage detector coupling a first input node and a second input node to and an output node;
• an input line coupled to the first input node of the peak voltage detector;
• a first electrically actuated switch coupled to the second input node of the peak voltage detector;
• a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor,
• wherein the first electrically actuated switch and the second electrically actuated switch are configured in a half-bridge arrangement, and the first electrically actuated switch directly couples the capacitor to the second input node of the peak voltage detector;
• wherein the first electrically actuated switch and the second electrically actuated switch each include a respective control node coupled to the input line, such that a signal in the input line enables current flow through the first electrically actuated switch and the second electrically actuated switch;
• a skewed buffer coupling the input line to the control node of the first electrically actuated switch and the control node of the second electrically actuated switch;
• and
• a reset transistor having a first source/drain terminal coupled to the second electrically actuated switch, a second source/drain terminal coupled to ground, and a gate terminal coupled to a reset line.