Flash memory device with three dimensional half flash structure and methods for forming the same

A method of forming a memory cell, comprising:

• forming a channel region in a substrate;
• forming a control gate dielectric layer of a gate structure on the channel region, wherein the control gate dielectric layer has a first length in a first direction;
• forming a control gate of the gate structure on the control gate dielectric layer, wherein the control gate has a second length in the first direction less than the first length;
• forming a second sidewall spacer on a second sidewall of the control gate and on the control gate dielectric layer;
• forming a first contact contacting the control gate dielectric layer over the channel region, having a height greater than a height of the control gate and including an outermost sidewall opposite the control gate and over the channel region;
• and
• forming an interlevel dielectric layer on opposing sides of the first contact such that the interlevel dielectric layer contacts the control gate dielectric layer at the sidewall spacer and over the channel region.

A memory device comprising:

• a plurality of memory cells arranged in a plurality of columns, wherein each memory cell of the plurality of memory cells comprises:
• a channel region in a substrate;
• a gate structure on the substrate, wherein the gate structure comprises:
• a control gate dielectric layer on the channel region and having a first length in a first direction;
• a control gate on the control gate dielectric layer and having a second length in the first direction less than the first length;
• and
• a second sidewall spacer on a second sidewall of the control gate and on the control gate dielectric layer;
• a first contact contacting the control gate dielectric layer over the channel region, having a height greater than a height of the control gate and including an outermost sidewall opposite the control gate and over the channel region;
• and
• an interlevel dielectric layer on opposing sides of the first contact and contacting the control gate dielectric layer at the second sidewall spacer and over the channel region;
• and
• a plurality of isolation regions alternatingly formed with the plurality of columns in the first direction.