Semiconductor device structure with etch stop layer for reducing RC delay

A semiconductor device structure, comprising:

• a substrate;
• a gate structure over the substrate;
• a spacer element covering a first sidewall of the gate structure;
• a source/drain portion in the substrate, wherein the spacer element separates the source/drain portion from the gate structure;
• a nitride layer over the source/drain portion and having a second sidewall, wherein the second sidewall faces the spacer element;
• a silicon layer over the nitride layer and having a third sidewall, wherein a topmost surface of the silicon layer is closer to the source/drain portion than a topmost surface of the spacer element, the third sidewall faces the spacer element, and the second sidewall is under and connected to the third sidewall;
• and
• a dielectric layer over the silicon layer, wherein the dielectric layer has a fourth sidewall and a bottom surface, the silicon layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the fourth sidewall, the second sidewall, and the third sidewall.

A semiconductor device structure, comprising:

• a substrate;
• a gate structure over the substrate;
• a spacer element covering a first sidewall of the gate structure;
• a nitride layer over the substrate and having a second sidewall;
• a silicon layer over the nitride layer and having a third sidewall, wherein a topmost surface of the silicon layer is lower than a topmost surface of the gate structure;
• and
• a dielectric layer over the silicon layer and having a fourth sidewall and a bottom surface, wherein the silicon layer is in direct contact with the bottom surface, and the second sidewall, the third sidewall, and the fourth sidewall are in direct contact with the spacer element.