HEMT transistor including field plate regions and manufacturing process thereof

A device, comprising:

• a semiconductor body having a semiconductive heterostructure;
• a conductive gate region on the semiconductor body;
• a first insulating layer on the semiconductor body, at least a portion of the conductive gate region extending through a first opening in the first insulating layer;
• a second insulating layer on the first insulating layer and the conductive gate region;
• a first conductive field plate extending between and in contact with the first and the second insulating layers, the first conductive field plate spaced laterally apart from the conductive gate region along a first direction;
• a second conductive field plate on the second insulating layer, the second conductive field plate overlying the first conductive field plate along a second direction transverse to the first direction, the second insulating layer extending directly between the first conductive field plate and the second conductive field plate along the second direction, wherein the second insulating layer is in contact with a top surface of the conductive gate region and a top surface of the first conductive field plate;
• and
• a dielectric layer extending between the first and the second insulating layers, wherein the dielectric layer has a second opening, wherein the conductive gate region includes a lower gate portion in the opening and in contact with the semiconductor body, a first intermediate gate portion between the first insulating layer and the dielectric layer, a second intermediate gate portion in the second opening above the first intermediate gate portion, and an upper gate portion above the second opening, wherein the first intermediate gate portion is wider in the first direction than the second intermediate gate portion.

A device, comprising:

• a semiconductor body including a semiconductor heterostructure;
• a first insulating layer on the semiconductor body and having a first opening and a recess spaced laterally apart from the first opening;
• a gate region, of conductive material, on the first insulating layer and in contact with the semiconductor body through the first opening;
• a first field plate region, of conductive material, on the first insulating layer, the first field plate region spaced laterally apart from the gate region and positioned in the recess;
• a second insulating layer over the gate region, the first field plate region, and the first insulating layer;
• and
• a second field plate region over the second insulating layer and the first field plate region, wherein the second insulating layer is in contact with a top surface of the gate region and a top surface of the first field plate region, wherein the gate region includes a lower gate portion and an upper gate portion, the lower gate portion extending into the first opening of the first insulating layer and in contact with the semiconductor body;
• and
• a dielectric layer extending between the first and the second insulating layers, wherein the dielectric layer has a second opening and a third opening, the gate region having an intermediate gate portion extending into the second opening, between the upper gate portion and the lower gate portion, and wherein the first field plate region has a lower plate portion extending through the third opening of the dielectric layer and in the recess of the first insulating layer, a reduced thickness portion of the first insulating layer extending between the lower plate portion and the semiconductor body.