Spacer structure for semiconductor device

A method, comprising:

• forming first and second sacrificial layers over a substrate;
• forming a recess structure to expose the first and second sacrificial layers;
• selectively etching the exposed first sacrificial layer over the exposed second sacrificial layer;
• and
• forming an inner spacer layer to cap the etched first sacrificial layer over the exposed second sacrificial layer.

A method, comprising:

• forming a first sacrificial layer on a substrate;
• forming a stack of nanostructured layers and second sacrificial layers in an alternating configuration on the first sacrificial layer;
• forming a polysilicon structure on the stack of nanostructured layers and second sacrificial layers;
• forming an opening extending through the stack of nanostructured layers and second sacrificial layers and through the first sacrificial layer;
• replacing the first sacrificial layer entirely with a dielectric layer;
• forming a source/drain region in the opening;
• and
• replacing the polysilicon structure and the second sacrificial layers with a gate structure.