Nanostructures formed over a substrate and a gate structure wrapping around the nanostructures

A method for forming a semiconductor device structure, comprising:

• forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction;
• forming a dielectric feature between the first fin structure and the second fin structure;
• forming a hard mask layer over the first fin structure and the second fin structure;
• patterning the hard mask layer to form a trench;
• forming a gate spacer layer in the trench;
• forming a dummy gate electrode layer in the trench and on the gate spacer layer;
• removing the hard mask layer;
• removing the dummy gate electrode layer to form trench;
• removing the second semiconductor layers to form a gap;
• and
• forming a gate structure in the trench and the gap.

A method for forming a semiconductor device structure, comprising:

• forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction;
• forming a first oxide layer over the first fin structure and the second fin structure;
• forming a hard mask layer on the first oxide layer;
• patterning the hard mask layer to form a trench;
• removing a portion of the first oxide layer exposed by the trench;
• forming a gate spacer layer in the trench;
• forming a dummy gate electrode layer in the trench and on the gate spacer layer;
• removing the hard mask layer;
• and
• replacing the dummy gate electrode layer with a gate structure.