Display panel, display panel manufacturing method, and display device

A display device, comprising a display panel, wherein the display panel comprises:

• a substrate;
• a buffer layer, formed on the substrate;
• a semiconductor layer, formed on the buffer layer, wherein the semiconductor layer comprises a source region, a drain region, and a channel region, and the channel region is arranged between the source region and the drain region;
• a gate insulating layer, formed at a position corresponding to the channel region of the semiconductor layer;
• a gate metal layer, formed on the gate insulating layer;
• and
• a dielectric layer, which is a single layer, wherein the dielectric layer covers the buffer layer, the semiconductor layer, and the gate metal layer, wherein the dielectric layer correspondingly covering the source region and the drain region defines via holes separately, the via holes each comprise a first via hole and a second via hole, the first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole;
• wherein a step is formed at a junction of the first via hole and the second via hole;
• wherein the first via hole and the second via hole are coaxial;
• wherein both the first via hole and the second via hole are cylindrical holes.

A display panel, comprising:

• a substrate;
• a buffer layer, formed on the substrate;
• a semiconductor layer, formed on the buffer layer, wherein the semiconductor layer comprises a source region, a drain region, and a channel region, and the channel region is arranged between the source region and the drain region;
• a gate insulating layer, formed at a position corresponding to the channel region of the semiconductor layer;
• a gate metal layer, formed on the gate insulating layer;
• and
• a dielectric layer, which is a single layer, wherein the dielectric layer covers the buffer layer, the semiconductor layer, and the gate metal layer, wherein the dielectric layer correspondingly covering the source region and the drain region defines via holes separately, the via holes each comprise a first via hole and a second via hole, the first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole;
• wherein a step is formed at a junction of the first via hole and the second via hole;
• wherein the aperture of the first via hole gradually increases from the respective source region or drain region to the top of the first via hole;
• and the aperture of the second via hole gradually increases from the top of the first via hole to the top of the second via hole.