Power semiconductor device and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSunkyu Hwang, Jongseob Kim
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a power semiconductor device includes forming a channel separation pattern on a substrate; forming a passivation layer on the substrate and the channel separation pattern; forming a gate hole, a source hole, and a drain hole penetrating the passivation layer in a same process step; and simultaneously forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern. The gate electrode pattern may be formed on the channel separation pattern. A side surface of the gate electrode pattern and a side surface of the channel separation pattern may have a step difference.
Claims20
A method of manufacturing a power semiconductor device, the method comprising:
- forming a channel separation pattern on a substrate;
- forming a passivation layer on the substrate and the channel separation pattern;
- and
- forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern penetrating the passivation layer in a same process step,
- wherein the gate electrode pattern is formed on the channel separation pattern, and
- a side surface of the gate electrode pattern and a side surface of the channel separation pattern have a step difference.
A power semiconductor device comprising:
- a substrate including a channel;
- a channel separation pattern on the substrate;
- a passivation layer on the substrate and the channel separation pattern, the passivation layer including a gate hole, a source hole, and a drain hole penetrating the passivation layer;
- and
- a gate electrode pattern, a source electrode pattern, and a drain electrode pattern in the gate hole, the source hole, and the drain hole, respectively, and extending onto an upper surface of the passivation layer, wherein a side surface of the gate electrode pattern in the gate hole and a side surface of the channel separation pattern have a step difference, and
- wherein the gate electrode pattern, the source electrode pattern, and the drain electrode pattern include a same conductive material.
A power semiconductor device comprising:
- a substrate including a channel;
- a channel separation pattern on the substrate;
- a passivation layer on the substrate and the channel separation pattern, the passivation layer including a gate hole, a source hole, and a drain hole penetrating the passivation layer;
- and
- a gate structure, a source electrode pattern, and a drain electrode pattern in the gate hole, the source hole, and the drain hole, respectively, and extending onto an upper surface of the passivation layer,
- wherein a width of a bottom surface of the gate structure in a first direction is less than a width of an upper surface of the channel separation pattern in the first direction,
- wherein the gate structure includes a gate electrode pattern,
- wherein the gate electrode pattern, the source electrode pattern, and the drain electrode pattern include a same conductive material, and
- the source electrode pattern does not vertically overlap the gate electrode pattern.
Dependencies are inferred from the claim text.