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US 12,218,202 B2Granted
Semiconductor device incorporating a substrate recess
AssigneeWolfspeed, Inc.
InventorsEvan Jones, Saptha Sriram, Kyle Bothe
Life of this patent
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Abstract
A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.
Claims13
A semiconductor device comprising:
- a substrate, wherein an upper surface of the substrate comprises a recess region;
- a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region;
- and
- a gate contact, a drain contact, and a source contact on the semiconductor structure,
- wherein the recess region is in between the gate contact and the source contact and does not vertically overlap the drain contact,
- wherein the semiconductor device comprises a high electron mobility transistor (HEMT) and the semiconductor structure comprises a channel layer and a barrier layer on the channel layer, and the channel layer extends continuously from underneath the source contact to underneath the drain contact,
- wherein the portion of the semiconductor structure that is within the recess region is an undoped Group III-nitride layer, and
- wherein the substrate comprises an n-type semiconductor substrate that includes a p-type impurity region adjacent the recess region.
5 more elements
A semiconductor device comprising:
- a substrate, wherein an upper surface of the substrate comprises a recess region;
- a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region;
- and
- a gate contact, a drain contact, and a source contact on the semiconductor structure,
- wherein the substrate and the portion of the semiconductor structure within the recess region form a heterojunction,
- wherein the semiconductor device is configured so that a two-dimensional electron gas (“2DEG”) layer that extends continuously from underneath the source contact to underneath the drain contact is induced in the semiconductor structure during on-state operation,
- wherein the recess region does not vertically overlap any of the source contact, the gate contact or the drain contact
- wherein portions of the substrate that comprise sidewalls of the recess region and a bottom of the recess region are implanted with first conductivity type dopants.
5 more elements
Dependencies are inferred from the claim text.