Semiconductor device and method

A device comprising:

• a first nanostructure and a second nanostructure over a substrate, the second nanostructure being over the first nanostructure, the first nanostructure comprising a first channel region, the second nanostructure comprising a second channel region;
• a first gate dielectric layer on the first channel region and the second channel region;
• a first work function tuning layer on the first gate dielectric layer, the first work function tuning layer extending from the first gate dielectric layer on the first channel region to the first gate dielectric layer on the second channel region, the first work function tuning layer comprising a first n-type work function metal, aluminum, and carbon, wherein the first n-type work function metal comprises zirconium;
• a first barrier layer on the first work function tuning layer;
• a glue layer on the first barrier layer;
• and
• a fill layer on the glue layer.

A method comprising:

• forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region and a second channel region, the second set of nanostructures comprising a third channel region and a fourth channel region;
• forming a gate dielectric layer having a first portion and a second portion, the first portion deposited on the first and second channel regions, the second portion deposited on the third and fourth channel regions;
• forming an n-type work function tuning layer on the first portion of the gate dielectric layer and the second portion of the gate dielectric layer, the n-type work function tuning layer extending from the gate dielectric layer on the first channel region to the gate dielectric layer on the second channel region, wherein the n-type work function tuning layer comprises zirconium aluminum carbide, hafnium aluminum carbide, niobium aluminum carbide, or combinations thereof;
• forming a first barrier layer on the n-type work function tuning layer;
• removing the first barrier layer and the n-type work function tuning layer from the second portion of the gate dielectric layer;
• forming a p-type work function tuning layer on the first barrier layer on the first set of nanostructures and the second portion of the gate dielectric layer, the p-type work function tuning layer extending from the gate dielectric layer on the third channel region to the gate dielectric layer on the fourth channel region;
• and
• forming a fill layer on the p-type work function tuning layer.