Gate oxide of nanostructure transistor with increased corner thickness

A device comprising:

• a semiconductor nanostructure;
• an oxide layer comprising:
• horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, wherein the horizontal portions have a first thickness;
• vertical portions on sidewalls of the semiconductor nanostructure, wherein the vertical portions have a second thickness;
• and
• corner portions on corners of the semiconductor nanostructure, wherein the corner portions have a third thickness, and wherein both of the second thickness and the third thickness are greater than the first thickness;
• a high-k dielectric layer surrounding the oxide layer;
• and
• a gate electrode surrounding the high-k dielectric layer.

A device comprising:

• a nano-FET comprising:
• a plurality of semiconductor strips, wherein higher ones of the plurality of semiconductor strips overlap corresponding lower ones of the plurality of semiconductor strips, and the plurality of semiconductor strips are vertically spaced apart from each other by spaces;
• a plurality of oxide layers, each wrapping around one of the plurality of semiconductor strips, wherein one of the plurality of oxide layers comprises:
• a first portion having a first thickness;
• and
• a second portion having a second thickness, wherein a ratio of the second thickness to the first thickness is greater than about 1.5:
• a high-k dielectric layer wrapping around each of the plurality of oxide layers;
• a gate electrode wrapping around the high-k dielectric layer;
• and
• a gate spacer contacting a sidewall of the high-k dielectric layer, wherein a first part of the gate spacer contacting the high-k dielectric layer is oxidized more than a second part of the gate spacer, with the second part being spaced apart from the high-k dielectric layer by the first part.