Back-end-of-line passive device structure having common connection to ground

A device structure, comprising:

• a capacitor stack, the capacitor stack comprising a plurality of conductor plate layers interleaved by a plurality of insulator layers, the capacitor stack including a first region and a second region, the first region and the second region overlapping in a third region;
• a first via passing through the first region;
• a second via passing through the second region;
• and
• a ground via passing through the third region,
• wherein the first via is capacitively coupled to the ground via at a first capacitance,
• wherein the second via is capacitively coupled to the ground via at a second capacitance different from the first capacitance.

A structure, comprising:

• a first transistor and a second transistor;
• a metal-insulator-metal (MIM) stack disposed over the first transistor and the second transistor, the MIM stack including a first region and a second region, the first region and the second region overlapping in a third region;
• a first via passing through the first region and electrically coupled to a source/drain feature of the first transistor;
• a second via passing through the second region and electrically coupled to a source/drain feature of the second transistor;
• and
• a ground via passing through the third region and electrically coupled to a ground potential,
• wherein the first via is capacitively coupled to the ground via at a first capacitance,
• wherein the second via is capacitively coupled to the ground via at a second capacitance different from the first capacitance.