Semiconductor device with multiple zero differential transconductance and method of manufacturing same

A semiconductor device with multiple zero differential transconductance, the semiconductor device comprising:

• a conductive substrate;
• a first insulating layer and a second insulating layer disposed on the conductive substrate;
• a first semiconductor and a second semiconductor disposed on upper portions of the first insulating layer and the second insulating layer, respectively, the first semiconductor and the second semiconductor comprising electrode contact areas;
• a first buffer layer and a second buffer layer disposed on the electrode contact areas of the first semiconductor and the second semiconductor, respectively;
• and
• an anode electrode and a cathode electrode disposed on the upper portions of the first insulating layer and the second insulating layer where the first semiconductor and the second semiconductor are not formed, and on surfaces of the first buffer layer and the second buffer layer,
• wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode,
• wherein the anode electrode connects to the first buffer layer and the second buffer layer, and the cathode electrode connects to the first buffer layer and the second buffer layer, and
• wherein the semiconductor device further comprises a plurality of drain current saturation regions in which the drain current is constant with respect to a change of gate voltage such that the semiconductor device has a plurality of stable logic states.