Dual gate array substrate and display panel

A dual gate array substrate, comprising a plurality of groups of dual gate lines, a plurality of data lines and a plurality of pixel pairs arranged on a first substrate;

• each group of the plurality of groups of dual gate lines comprising two gate lines opposite to each other;
• the plurality of groups of dual gate lines intersecting with the plurality of data lines;
• each group of dual gate lines and the plurality of data lines defining a plurality of defined regions;
• each pixel pair being in a corresponding defined region;
• the pixel pair comprising two pixel units arranged along an extending direction of the gate line;
• the pixel unit comprising a common electrode and a thin film transistor,
• wherein the dual gate array substrate further comprises a plurality of common electrode lines, each of the plurality of common electrode lines is arranged between two pixel units in a same pixel pair;
• and
• a layer where the common electrode line is located and a layer where a source/drain electrode of the thin film transistor is located are different layers and insulated from each other,
• wherein the two pixel units in the same pixel pair are connected to a same data line;
• in two pixel pairs adjacent to each other in an extending direction of the data line, the pixel units in different pixel pairs are connected to two adjacent data lines, respectively;
• and
• in two pixel pairs adjacent to each other in the extending direction of the gate line, the pixel units in different pixel pairs are connected to two adjacent data lines, respectively.