Connection structure for LCD clock circuit

An array substrate, comprising:

• a base substrate;
• a first conductive layer on a side of the base substrate, comprising a plurality of first wires, wherein the first wires are clock wires in a gate drive circuit;
• a second conductive layer on a side of the base substrate, comprising a plurality of second wires, the first conductive layer and the second conductive layer being located in different layers, the plurality of second wires having at least a first length and a second length, the first length being less than the second length, wherein the second wires are clock lead wires in the gate drive circuit;
• and
• a third conductive layer on a side of the base substrate, comprising a plurality of connecting electrodes, and the connecting electrodes being respectively connected to the first wires and the second wires so as to connect corresponding first wires and second wires, an orthographic projection, on the base substrate, of a connecting electrode connected to a second wire having the first length having a first area, and an orthographic projection, on the base substrate, of a connecting electrode connected to a second wire having the second length having a second area;
• wherein the first area is greater than the second area.