Hybrid fin field-effect transistor cell structures and related methods

A circuit cell for a flip-flop, comprising:

• a first stage configured to receive a flip-flop input and pass the flip-flop input through to a first stage output in response to a signal, the first stage including field-effect transistors (finFETs) formed in one of a first fin portion of the circuit cell or a second fin portion of the circuit cell based on a performance optimization criterion, wherein the first fin portion of the circuit cell includes a first plurality of fin structures arranged in a plurality of first rows, and the second fin portion of the circuit cell includes a second plurality of fin structures arranged in a plurality of second rows, wherein each of the second rows, in the second fin portion, contain a lesser number of fin structures than each of the first rows, in the first fin portion of the circuit cell;
• a second stage connected to the first stage and configured to receive the first stage output and generate a first latched output in response to the signal, the second stage including finFETs in a forward path that are formed in the first fin portion of the circuit cell and finFETs in a feedback path that are formed in the second fin portion of the circuit cell;
• and
• a third stage configured to generate a second stage output and including finFETs formed in the first fin portion, the second fin portion, or the first and second fin portions.

A circuit cell for a multiplexer, comprising:

• a first stage configured to receive a first input signal and including a plurality of fin field-effect transistors (finFETs) formed in a first row;
• a second stage configured to receive a select signal and including a plurality of finFETs formed in a second row, wherein the first row has a greater number of fin structures than the second row;
• and
• a third stage configured to provide a stage output and including finFETs formed in the first row, the second row, or the first and second rows.