Three-dimensional semiconductor device and method of fabricating the same

A three-dimensional semiconductor device, comprising:

• a first active region on a substrate and a second active region on the first active region;
• a first gate electrode and a second gate electrode on the first active region and the second active region,
• wherein the first gate electrode includes
• a first lower gate electrode on the first active region,
• a first upper gate electrode on the second active region, and
• a first isolation pattern between the first lower gate electrode and the first upper gate electrode, and
• wherein the second gate electrode includes
• a second lower gate electrode on the first active region,
• a second upper gate electrode on the second active region, and
• a second isolation pattern between the second lower gate electrode and the second upper gate electrode;
• a first upper gate contact coupled to the first upper gate electrode;
• a first lower gate contact coupled to the first lower gate electrode;
• a second upper gate contact coupled to the second upper gate electrode;
• a second lower gate contact coupled to the second lower gate electrode;
• a first wiring line electrically connected to the first upper gate contact and the second lower gate contact;
• and
• a second wiring line electrically connected to the first lower gate contact and the second upper gate contact.

A three-dimensional semiconductor device, comprising:

• a first active region on a substrate, the first active region including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern;
• a second active region on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern;
• a dummy channel pattern between the lower channel pattern and the upper channel pattern;
• and
• a gate electrode on the lower channel pattern, the dummy channel pattern, and the upper channel pattern,
• wherein the gate electrode includes:
• a lower gate electrode on the lower channel pattern;
• an upper gate electrode on the upper channel pattern;
• and
• an isolation pattern between the lower gate electrode and the upper gate electrode.