US 12,218,122 B2 · Read-only memory circuit

Abstract

A memory circuit includes first and second read-only memory (ROM) cells aligned along a first active structure including a first shared source portion of the first and second ROM cells, third and fourth ROM cells aligned along a second active structure including a second shared source portion of the third and fourth ROM cells, a first bit line overlying the first and second ROM cells, a second bit line overlying the third and fourth ROM cells, and a reference voltage line positioned between the first and second bit lines and in a same metal layer as the first and second bit lines. A conductive structure is electrically connected to each of the first and second shared source portions and the reference voltage line and is positioned in a metal layer below the same metal layer.

Claims20

Dependent claims

A memory circuit comprising:

first and second read-only memory (ROM) cells aligned along a first active structure comprising a first shared source portion of the first and second ROM cells;
third and fourth ROM cells aligned along a second active structure comprising a second shared source portion of the third and fourth ROM cells;
a first bit line overlying the first and second ROM cells;
a second bit line overlying the third and fourth ROM cells;
a reference voltage line positioned between the first and second bit lines and in a same metal layer as the first and second bit lines;
and
a conductive structure electrically connected to each of the first and second shared source portions and the reference voltage line,
wherein the conductive structure is positioned in a metal layer below the same metal layer.

5 more elements

A memory circuit comprising:

first and second read-only memory (ROM) cells aligned along a first active structure comprising a first shared source portion of the first and second ROM cells;
third and fourth ROM cells aligned along a second active structure comprising a second shared source portion of the third and fourth ROM cells;
a first bit line overlying the first and second ROM cells;
a second bit line overlying the third and fourth ROM cells;
a reference voltage line positioned between the first and second bit lines and in a same metal layer as the first and second bit lines;
a first conductive structure positioned on the first shared source portion;
a second conductive structure positioned on the second shared source portion;
and
a third conductive structure electrically connected to each of the first and second conductive structures and the reference voltage line,
wherein the first through third conductive structures are positioned in metal layers below the same metal layer.

7 more elements

A memory circuit comprising:

first and second read-only memory (ROM) cells aligned along a first active structure comprising a first shared source portion of the first and second ROM cells;
third and fourth ROM cells aligned along a second active structure comprising a second shared source portion of the third and fourth ROM cells;
a first gate structure included in each of the first and third ROM cells;
a second gate structure included in each of the second and fourth ROM cells;
a first bit line overlying the first and second ROM cells;
a second bit line overlying the third and fourth ROM cells;
a reference voltage line positioned between the first and second bit lines and in a same metal layer as the first and second bit lines;
and
a first conductive structure positioned between the first and second gate structures and electrically connected to each of the first and second shared source portions and the reference voltage line,
wherein the first conductive structure is positioned in a metal layer below the same metal layer.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/363,171Filed 1 Aug 2023 · continuation

Priority

30 Jan 2015

Published

US 2023/0378160 A123 Nov 2023

Granted

4 Feb 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
H10B 20/34
Having the source region and the drain region on the same level, e.g. lateral transistors: source electrode or drain electrode programmed
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs

Family

Application14/610,158Parent of this division · filed 30 Jan 2015

Application15/863,090Parent of this division · filed 5 Jan 2018

US 9,887,186 B2Parent of this division · filed 6 Feb 2018

Application16/688,696Parent of this continuation · filed 19 Nov 2019

US 10,490,544 B2Parent of this division · filed 26 Nov 2019

Application17/323,467Parent of this continuation · filed 18 May 2021

US 11,024,621 B2Parent of this continuation · filed 1 Jun 2021

US 2023/0378160 A1Pre-grant publication · published 23 Nov 2023

US 11,764,202 B2Parent of this continuation

Application16/688,696Parent of this division

US 2016/0225753 A1Published application

US 2018/0130787 A1Published application

US 2020/0091133 A1Published application

US 2021/0272947 A1Published application

US 12,218,122 B2This patent

From the US filing history. Foreign family members aren’t listed.

Read-only memory circuit

Life of this patent

Read-only memory circuit

Life of this patent

Abstract

Claims20