Back to results
US 12,218,119 B2Granted
Stacked interposer structures
AssigneeMicron Technology, Inc.
InventorsOwen R. Fay, Chan H. Yoo
Life of this patent
Estimating the term…
Abstract
An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
Claims9
A stacked interposer structure, comprising:
- a first interposer comprising:
- a first core comprising a semiconductor material;
- a first redistribution structure comprising multiple redistribution layers (RDLs) over a side of the first core, the first redistribution structure configured for operably coupling, on a surface of the first redistribution structure, to one or more memory device stack locations and to a processor device location;
- cache memory at least partially within the first core adjacent the first redistribution structure under and operably coupled through the first redistribution structure to the processor device location;
- and
- a first set of through silicon vias (TSVs) extending from the first redistribution structure through the first core to an opposite side of the first core;
- and
- a second interposer comprising:
- a second core comprising a semiconductor material;
- a second redistribution structure comprising multiple redistribution layers (RDLs) over a side of the second core;
- a second set of through silicon vias (TSVs) extending from the second redistribution structure through the second core to an opposite side of the second core;
- the first interposer and the second interposer being oriented with the first redistribution structure and the second redistribution structure facing in a common direction;
- and
- the first and second redistribution structures being operably coupled through only one of the first set of TSVs and the second set of TSVs.
11 more elements
A stacked interposer structure, comprising:
- an interposer comprising:
- a silicon core;
- at least one of active circuitry and passive circuitry over an active surface of the silicon core;
- a redistribution structure comprising at least four redistribution layers (RDLs) located over the at least one of the active circuitry and the passive circuitry;
- cache memory within the silicon core adjacent and under the redistribution structure and operably coupled to a processor device location on and through the redistribution structure;
- and
- through silicon vias (TSVs) operably coupled to at least the redistribution structure and extending through the silicon core to a side thereof opposite the redistribution structure;
- and
- an additional interposer comprising:
- an additional silicon core;
- an additional redistribution structure comprising additional RDLs over a side of the additional silicon core;
- and
- additional TSVs extending from the additional redistribution structure through the additional silicon core to an opposite side of the additional silicon core;
- the redistribution structure and the additional redistribution structure being operably coupled through only one of the TSVs and the additional TSVs.
11 more elements
Dependencies are inferred from the claim text.