Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate

An electronic module, comprising:

• a first substrate;
• a first dielectric layer on the first substrate;
• an electronic chip, which is mounted with a first main surface directly or on a section of the first dielectric layer;
• a second substrate over a second main surface of the at least one electronic chip;
• an electrical contacting for electrically contacting a first pad of the at least one electronic chip on the first main surface of the at least one electronic chip through the first dielectric layer,
• wherein the first dielectric layer on the first substrate extends across an area, which exceeds the first main surface;
• a second dielectric layer on the second substrate, wherein the electronic chip is mounted with its second main surface directly on a section of the second dielectric layer;
• a further electrical contacting for electrically contacting a second pad of the at least one electronic chip on the second main surface of the at least one electronic chip through a plurality of clearance holes penetrating the second dielectric layer;
• a dielectric structure, in particular a laminate structure, to fill in completely at least one hollow space, which is delimited between the first dielectric layer, the second dielectric layer and the at least one electronic chip;
• wherein at least one of the first substrate and of the second substrate is a structured foil, and
• wherein the first dielectric layer is formed by a first partial layer on the first substrate and a separate second partial layer on the first partial layer where the first partial layer is between the first substrate and the second partial layer, the first partial layer and the second partial layer comprising different material compositions.

An electronic module comprising:

• a dielectric structural layer;
• a chip embedded in the dielectric structural layer, the chip including a first main surface and a second main surface;
• a first dielectric layer positioned over the dielectric structural layer and extending partially over the first main surface;
• an electrical contacting for electrically contacting a first pad of the chip on the first main surface of the chip through plurality of clearance holes penetrating the first dielectric layer;
• an electrically conductive first substrate positioned on the first dielectric layer and the first main surface,
• where the dielectric structural layer extends beyond and partially covers the second main surface, and an electric contact via extending through the structural layer for electrically contacting a second pad of the chip on the second main surface of the chip;
• a second dielectric layer positioned over the dielectric structural layer, where the second dielectric layer partially extends into the via;
• and
• an electrically conductive second substrate positioned over the second dielectric layer,
• wherein the first dielectric layer is formed by a first partial layer over the dielectric structural layer and the first main surface and a separate second partial layer on the first partial layer where the first partial layer is between the first substrate and the second partial layer, the first partial layer and the second partial layer comprising different material compositions.