Semiconductor package and method of fabricating the same

A semiconductor package, comprising:

• a redistribution layer having a first surface and a second surface opposite to each other and including first redistribution pads on the first surface of the redistribution layer and first vias below the first redistribution pads;
• a semiconductor chip on the second surface of the redistribution layer, the semiconductor chip including chip pads facing the redistribution layer;
• conductive structures on the second surface of the redistribution layer and spaced apart from the semiconductor chip, each of the conductive structures including a conductive pad at one end;
• and
• a first semiconductor device on the first surface of the redistribution layer, the first semiconductor device including connection pads facing the redistribution layer,
• wherein the first redistribution pads are connected to the connection pads, respectively,
• wherein the conductive pads are arranged according to a first separation distance,
• wherein the first redistribution pads are arranged according to a second separation distance smaller than the first separation distance, and
• wherein the first redistribution pads do not overlap the semiconductor chip in a vertical direction,
• wherein the semiconductor chip includes first and second side surfaces opposite to each other, the first separation distance being defined as a distance between a pair of adjacent ones of the conductive pads positioned closer to the second side surface than to the first side surface of the semiconductor chip,
• wherein upper surfaces of the first vias are at the same vertical level as the first surface of the redistribution layer, and
• wherein each of the first redistribution pads contacts a corresponding one of the first vias.

A semiconductor package, comprising:

• a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including first redistribution pads on the first surface;
• a first semiconductor device on the first surface of the redistribution layer, the first semiconductor device being coupled to the first redistribution pads;
• a semiconductor chip on the second surface of the redistribution layer, the semiconductor chip including an active surface facing the redistribution layer, a first side surface, and a second side surface opposite the first side surface;
• a wiring substrate on the second surface of the redistribution layer and surrounding the semiconductor chip, the wiring substrate including a base layer and conductive structures, the conductive structures being spaced apart from the semiconductor chip, and each of the conductive structures including a conductive pad at one end;
• and
• external connection terminals on and coupled to the conductive pads of the conductive structures,
• wherein the conductive pads are arranged according to a first separation distance, and the first redistribution pads are arranged according to a second separation distance smaller than the first separation distance,
• wherein the first separation distance is defined as a distance between a pair of adjacent ones of the conductive pads positioned closer to the second side surface than to the first side surface of the semiconductor chip,
• wherein the second separation distance is defined as a distance between a pair of adjacent ones of the first redistribution pads,
• wherein the first semiconductor device and the semiconductor chip are connected to each other via the redistribution layer and the first redistribution pads on the first surface of the redistribution layer, and
• wherein all the first redistribution pads are in a region overlapped by the first semiconductor device.