Integrated chip with graphene based interconnect

A method for forming an integrated chip, the method comprising:

• depositing a plurality of graphene layers directly on a metal interconnect and a first dielectric layer that overlie a substrate;
• etching the plurality of graphene layers to form a first graphene stack from the plurality of graphene layers, a second graphene stack from the plurality of graphene layers, and a cavity laterally between the first graphene stack and the second graphene stack;
• intercalating a metal between graphene layers of the first graphene stack to form a first wire from the first graphene stack and the metal, and intercalating the metal between graphene layers of the second graphene stack to form a second wire from the second graphene stack and the metal, wherein the intercalated metal and graphene of the first wire is directly on the metal interconnect and the first dielectric layer;
• depositing a second dielectric layer over the first wire, the second wire, and the cavity, wherein the second dielectric layer seals the cavity;
• and
• planarizing the second dielectric layer to form a dielectric cap from the second dielectric layer and to uncover top surfaces of the first wire and the second wire, the dielectric cap disposed between the first wire and the second wire and over the cavity.

A method for forming an integrated chip, the method comprising:

• forming a semiconductor device along a substrate;
• forming a first wire over and coupled to the semiconductor device, the first wire comprising a first metal and a first stack of graphene sheets, wherein the first metal is intercalated between sheets of the first stack of graphene sheets;
• forming a metal via within a first dielectric layer over the first wire, the metal via coupled to the first wire;
• depositing a second stack of graphene sheets directly on an upper surface of the metal via and an upper surface of the first dielectric layer;
• patterning the second stack of graphene sheets to form a cavity between a first segment of the second stack of graphene sheets and a second segment of the second stack of graphene sheets;
• depositing a second metal between graphene sheets of the first segment of the second stack of graphene sheets and between graphene sheets of the second segment of the second stack of graphene sheets to form a second wire from the first segment of the second stack of graphene sheets and the second metal and a third wire from the second segment of the second stack of graphene sheets and the second metal;
• depositing a second dielectric layer over the second wire, the third wire, and the cavity, wherein the cavity is delimited by a lower surface of the second dielectric layer;
• and
• removing the second dielectric layer from over the second wire and the third wire to uncover the second wire and the third wire, wherein a portion of the second dielectric layer remains over the cavity and seals the cavity.