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US 12,218,056 B2Granted
Component inter-digitated vias and leads
AssigneeMicron Technology, Inc.
InventorChristopher Kinney
Life of this patent
Estimating the term…
Abstract
Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).
Claims8
A method of reducing inductance on an integrated circuit package, the method comprising:
- configuring the integrated circuit package to support a plurality of electrical contacts that comprise a set of power leads and a set of ground leads, the set of power leads comprising a first power lead and a second power lead, and the set of ground leads including at least a ground lead;
- and
- arranging the plurality of electrical contacts upon the integrated circuit package in an alternating arrangement of power leads and ground leads to form an inter-digitated arrangement that comprise a first gap between the first power lead and the second power lead, and a second gap between the first power lead and the ground lead, the first gap being greater than the second gap.
Dependencies are inferred from the claim text.