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US 12,218,052 B2Granted
Advanced lithography and self-assembled devices
AssigneeIntel Corporation
InventorsRichard E. Schenker, Robert L Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
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Abstract
Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
Claims20
A method of fabricating an integrated circuit structure, the method comprising:
- forming a plurality of backbone features above a semiconductor substrate, a semiconductor layer, or a stack of semiconductor layers;
- forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different than a material composition of the plurality of backbone features;
- forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different than the first material composition and different than the material composition of the plurality of backbone features;
- subsequent to forming the second set of spacers, removing the plurality of backbone features;
- subsequent to removing the plurality of backbone features, forming a third set of spacers along sidewalls of each of the first set of spacers, the third set of spacers having the second material composition;
- forming a final feature in each opening between adjacent pairs of spacers of the third set of spacers;
- planarizing the first set of spacers, the second set of spacers, the third set of spacers, and the final features to form a target foundation layer;
- and
- using the target foundation layer to form a plurality of fins or three-dimensional bodies in the semiconductor substrate, the semiconductor layer, or the stack of semiconductor layers.
6 more elements
A method of fabricating an integrated circuit structure, the method comprising:
- forming a plurality of backbone features above a semiconductor substrate, a semiconductor layer, or a stack of semiconductor layers;
- forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different than a material composition of the plurality of backbone features;
- forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different than the first material composition and different than the material composition of the plurality of backbone features;
- forming a third set of spacers along sidewalls of each of the second set of spacers, the third set of spacers having a third material composition different than the first material composition, different than the second material composition, and different than the material composition of the plurality of backbone features;
- forming a fourth set of spacers along sidewalls of each of the third set of spacers, the fourth set of spacers having the second material composition;
- forming a fifth set of spacers laterally adjacent to sidewalls of each of the fourth set of spacers, the fifth set of spacers having the first material composition;
- subsequent to forming the fifth set of spacers, removing the plurality of backbone features;
- subsequent to removing the plurality of backbone features, forming a sixth set of spacers along sidewalls of each of the first set of spacers and along sidewalls of each of the fifth set of spacers, the sixth set of spacers having the second material composition;
- forming a final feature in each opening between adjacent pairs of spacers of the sixth set of spacers;
- planarizing the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, the sixth set of spacers, and the final features to form a target foundation layer;
- and
- using the target foundation layer to form a plurality of fins or three-dimensional bodies in the semiconductor substrate, the semiconductor layer, or the stack of semiconductor layers.
9 more elements
Dependencies are inferred from the claim text.