Memory devices and methods of manufacturing thereof

A memory device layout, comprising:

• a first feature comprising:
• a first sub-feature extending along a first direction and configured to define a source and a drain of a first transistor, wherein the first sub-feature has a first width along a second direction perpendicular to the first direction;
• and
• a second sub-feature extending from the first sub-feature along the first direction and configured to define a source and a drain of a second transistor, wherein the second sub-feature has a second width along the second direction, and wherein the second width is greater than the first width.

A method for fabricating a semiconductor device, comprising:

• forming a plurality of first semiconductor nanostructures having a first width along a first lateral direction;
• forming a first gate metal extending along the first lateral direction and wrapping around each of the plurality of first semiconductor nanostructures;
• forming a plurality of second semiconductor nanostructures having a second, different width along the first lateral direction;
• forming a second gate metal extending along the first lateral direction and wrapping around each of the plurality of second semiconductor nanostructures;
• forming a first source/drain structure disposed on a first side of the first gate metal along a second lateral direction, and having the first width along the first lateral direction;
• forming a second source/drain structure disposed on a second side of the first gate metal along the second lateral direction, and having the first width along the first lateral direction;
• forming a third source/drain structure disposed on a first side of the second gate metal along the second lateral direction, and having a second width along the first lateral direction;
• and
• forming a fourth source/drain structure disposed on a second side of the second gate metal along the second lateral direction, and having the second width along the first lateral direction.