Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• transistors on a substrate;
• a first interlayer insulating layer on the transistors;
• a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer;
• a second interlayer insulating layer on the first interlayer insulating layer;
• and
• an upper interconnection line in the second interlayer insulating layer,
• wherein the upper interconnection line includes
• a line portion, and
• a bar via extending from the line portion to the first and second lower interconnection lines, the bar via including
• a first contact portion and a second contact portion connected to the first and second lower interconnection lines, respectively, and
• a connecting portion between the first and second contact portions, and
• wherein one of a first line width of the first lower interconnection line and a second line width of the line portion gradually decreases away from the substrate, and
• the other of the first line width and the second line width gradually increases away from the substrate.

A semiconductor device, comprising:

• a substrate including an active pattern;
• a plurality of channel patterns that are stacked on the active pattern and vertically spaced apart from each other;
• a source/drain pattern on the active pattern, the source/drain pattern being connected to the plurality of channel patterns;
• a gate electrode on the plurality of channel patterns, the gate electrode surrounding each of the plurality of channel patterns;
• an active contact electrically connected to the source/drain pattern;
• a gate contact electrically connected to the gate electrode;
• a first interlayer insulating layer on the active contact and the gate contact;
• a first lower interconnection line and a second lower interconnection line in the first interlayer insulating layer, the first and second lower interconnection lines being electrically connected to at least one of the gate contact and the active contact;
• an etch stop layer on the first and second lower interconnection lines;
• a second interlayer insulating layer on the etch stop layer;
• and
• an upper interconnection line in the second interlayer insulating layer,
• wherein the upper interconnection line includes
• a line portion, and
• a bar via extending from the line portion to the first and second lower interconnection lines to penetrate the etch stop layer, the bar via including
• a first contact portion and a second contact portion connected to the first and second lower interconnection lines, respectively, and
• a connecting portion between the first and second contact portions.