Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods

A method of fabricating an integrated circuit (IC) package, comprising:

• providing an IC chip comprising a plurality of die interconnects;
• forming a package substrate comprising a plurality of package substrate interconnects;
• forming a redistribution layer (RDL) substrate on the package substrate, comprising:
• forming a first RDL layer comprising one or more first RDL interconnects;
• forming a dielectric layer;
• disposing a capacitor package comprising a capacitor in the dielectric layer;
• forming a second RDL layer comprising one or more second RDL interconnects, wherein the dielectric layer is between the first RDL layer and the second RDL layer;
• forming one or more first vias each coupled to a first RDL interconnect of the one or more first RDL interconnects;
• and
• forming one or more second vias extending through the dielectric layer and extending through the capacitor package and each coupled to a first RDL interconnect of the one or more first RDL interconnects, and each coupled to a second RDL interconnect of the one or more second RDL interconnects;
• coupling each of the one or more first RDL interconnects to a die interconnect of the plurality of die interconnects of the IC chip;
• coupling each of the one or more second RDL interconnects to a package substrate interconnect of the plurality of package substrate interconnects;
• and
• forming a molding on the RDL substrate and the package substrate.