Semiconductor device with improved performance in operation and improved flexibility in the arrangement of power chips

A semiconductor device, comprising:

• an insulating interposer comprising an insulative layer disposed between a lower metal layer and a first upper metal layer;
• at least one semiconductor transistor die attached to the first upper metal layer, the semiconductor transistor die comprising a first lower main face and a second upper main face opposite to the first main face and a drain or collector electrode pad disposed on the first main face and electrically connected to the first upper metal layer of the insulating interposer, a source or emitter electrode pad disposed on the second main face, and a gate electrode pad disposed on the second main face;
• a leadframe connected to the insulating interposer, the leadframe comprising a plurality of leads,
• wherein a first lead is connected with the first upper metal layer of the insulating interposer, and a second lead is connected with the source electrode pad,
• wherein the semiconductor device is characterized by the insulating interposer comprising a second upper metal layer and the leadframe comprising a third lead which is connected with the second upper metal layer, and
• wherein an electrical connector is connected between the gate electrode pad and the second upper metal layer so that it extends in a direction which is essentially orthogonal to an extension direction of a first electrical connector.