Integrated circuit device

An integrated circuit device, comprising:

• an interconnect layer, wherein the interconnect layer has an interlayer dielectric layer and a conductive pad in the interlayer dielectric layer;
• a memory structure over and in contact with the conductive pad, wherein the memory structure comprises at least a resistance switching element over the conductive pad and a top electrode over the resistance switching element;
• and
• a first conductive line over and in direct contact with the top electrode, wherein the top electrode has a first portion overlapping the first conductive line and a second portion nonoverlapping the first conductive line, and the first and second portions of the top electrode are aligned with each other along a direction perpendicular to a lengthwise direction of the first conductive line in a top view.

An integrated circuit device, comprising:

• a semiconductor substrate;
• a transistor over the semiconductor substrate;
• a first interlayer dielectric layer surrounding the transistor;
• a first conductive via and a second conductive via in the first interlayer dielectric layer, wherein the first conductive via is laterally aligned with the second conductive via;
• a memory structure over and in direct contact with a top surface of the first conductive via, wherein the memory structure comprises at least a resistance switching element over the first conductive via and a top electrode over and in contact with the resistance switching element;
• a first conductive line over and in direct contact with a top surface of the second conductive via;
• a third conductive via over and in direct contact with a top surface of the first conductive line, wherein the first conductive line extends beyond an entire width of the third conductive via;
• a second conductive line over and in contact with the top electrode of the memory structure;
• and
• a fourth conductive via over and in direct contact with a top surface of the second conductive line, wherein the fourth conductive via is laterally aligned with the third conductive via, and the second conductive line extends beyond an entire width of the fourth conductive via.