Selective ILD deposition for fully aligned via with airgap

A method comprising:

• forming trenches within an insulating layer disposed over a semiconductor substrate;
• filling the trenches with conductive material to form conductive regions;
• selectively forming first dielectric regions on a pattern over exposed top surfaces of the insulating layer;
• forming a mask over the semiconductor substrate and removing the first dielectric regions in areas not covered by the mask;
• depositing an inter-layer dielectric over remaining first dielectric regions, the conductive regions, and the insulating layer;
• and
• etching a portion of the inter-layer dielectric between two of the remaining first dielectric regions to form a self-aligned via.