Memory array test structure and method of forming the same

A device comprising:

• a memory array including:
• a first word line in a first layer of the memory array, a second word line in a second layer of the memory array, the second layer vertically atop the first layer, and a third word line in a third layer of the memory array, the third layer being vertically atop the second layer, the first word line, the second word line, and the third word line extending in a first horizontal direction by a first length, by a second length less than the first length, and by a third length less than the second length, respectively;
• first memory films extending, respectively, along a first inner sidewall of the first word line, a second inner sidewall of the second word line, and a third inner sidewall of the third word line;
• a first channel region extending horizontally down the first, second, and third inner sidewalls, wherein respective first memory films are interjacent the first channel region and the first inner sidewall, the first channel region and the second inner sidewall, and the first channel region and the third inner sidewall;
• a first source line extending vertically through the memory array and contacting a first end of the first channel region;
• and
• a first bit line extending vertically through the memory array and contacting a second end of the first channel region, opposite the first end of the first channel region;
• and
• an interconnection structure including:
• a first contact, a second contact, and a third contact each extending vertically from a top of the memory array, and respectively contacting the first word line, the second word line, and the third word line.

A device, comprising:

• a three-dimensional memory array comprising a stack of layers, each layer including a plurality of parallel word lines and a plurality of memory cell between adjacent words, each word line in a layer of the stack of layers having the same length and each word line in a layer of the stack of layers having a length that is less than the length of each word line in a lower layer of the stack of layers;
• a plurality of vertically extending conductive vias, each vertically extending conductive via of the plurality of vertically extending conductive vias landing on one end of a respective word line of the plurality of parallel word lines of the stack of layers;
• and
• a test structure overlying the three-dimensional memory array, the test structure including first conductors electrically connecting respective word lines of a same layer of the stack of layers, and second conductors electrically connecting respective word lines in different layers of the stack of layers.