Memory device with source line control

A memory system:

• a memory array including:
• a first memory cell;
• a second memory cell;
• a first bit line coupled to the first memory cell and the second memory cell;
• and
• a first word line coupled to the first memory cell and the second memory cell;
• and
• a memory controller to:
• apply a first write voltage to the first bit line during a first time period to write data to the first memory cell;
• and
• apply a second write voltage to the first word line coupled to the first memory cell during the first time period,
• wherein a difference between the first write voltage and the second write voltage is less than an allowable stress voltage of a select transistor of the first memory cell, wherein the second write voltage is between the first write voltage and a third write voltage of a source line coupled to the first memory cell.

A method, comprising:

• applying, by a memory controller, a first write voltage to a bit line during a time period to write data to a selected memory cell, the bit line coupled to the selected memory cell and an unselected memory cell;
• and
• applying, by the memory controller, a second write voltage to a first word line coupled to the selected memory cell during the time period,
• wherein a difference between the first write voltage and the second write voltage is less than an allowable stress voltage of a select transistor of the selected memory cell, wherein the second write voltage is between the first write voltage and a third write voltage of a source line coupled to the selected memory cell.