Storage device and operating method with multiple channels

A storage device comprising:

• a memory device including a plurality of memory dies and a plurality of interfaces connected to the plurality of memory dies;
• and
• a memory controller configured to provide an address latch enable (ALE) signal, a command latch enable (CLE) signal, and a chip enable (CE) signal to the plurality of interfaces during a predetermined time,
• wherein the plurality of interfaces address a memory die among the plurality of memory dies by using an address value comprising a two bit combination of a logical value of the address latch enable signal and a logical value of the command latch enable signal.

A method of operating a storage device including a plurality of memory dies and a plurality of interfaces connected to the plurality of memory dies, the method comprising:

• addressing a memory die among the plurality of memory dies by using an address value comprising a two bit combination of a logical value of an address latch enable (ALE) signal and a logical value of a command latch enable (CLE) signal, which are input to the plurality of interfaces during predetermined N cycles, where N is a natural number;
• and
• controlling the memory die to perform a memory operation,
• wherein the addressing of the memory die includes addressing a channel corresponding to the memory die among a plurality of channels respectively connected to a plurality of package groups by using a logical value of a chip enable (CE) signal.

An operating method of a memory device, the operating method comprising:

• selecting, in response to an address value comprising a two bit combination of a logical value of a chip enable (CE) signal from a controller, a package group of a plurality of package groups included in the memory device;
• selecting sequentially, in response to respective toggles of a logical value of an address latch enable (ALE) signal and a logical value of a command latch enable (CLE) signal from the controller during first to third time periods, a memory package within the selected package group, an interface within the selected memory package and a memory die group coupled to the selected interface;
• and
• performing, in response to a combination of a data (DQ) signal and the ALE and CLE signals during a fourth time period, an operation on a memory die within the selected memory die group.