Counter circuit

A counter circuit, comprising:

• an addition circuit, a subtraction circuit and a plurality of control circuits, wherein:
• the addition circuit comprises multiple stages of counting circuits corresponding to binary bits, and each stage of counting circuit is configured to:
• obtain a carry signal and a this-time bit value according to an addend signal and a bit value that is currently output by the stage of counting circuit, output the carry signal to a next-stage counting circuit, latch the this-time bit value in response to a first clock, and output the this-time bit value to an output terminal of the stage of counting circuit in response to a second clock, wherein an addend signal of a start-stage counting circuit is a high-level signal, and an addend signal of a non-start-stage counting circuit is a carry signal output by an immediately previous stage of counting circuit;
• the subtraction circuit is connected to the multiple stages of counting circuits and is configured to:
• obtain a present subtraction counting result by calculating according to a present addition counting result and a subtrahend signal, and output the present subtraction counting result in response to a first refresh instruction, wherein the present addition counting result is a multi-bit signal composed of this-time bit values output by the multiple stages of counting circuits, and the present subtraction counting result comprises a multi-bit signal;
• and
• each of the plurality of control circuits corresponds to a respective one of the multiple stages of counting circuits, is connected to the respective one of the multiple stages of counting circuits and the subtraction circuit, and is configured to output, in response to a second refresh instruction, a corresponding bit of the present subtraction counting result to the respective one of the multiple stages of counting circuits to serve as the bit value output by the respective one of the multiple stages of counting circuits, wherein an output of the counter circuit is composed by bit values output by the multiple stages of counting circuits, the output is a binary representation of a counting result, the first clock and the second clock are obtained based on division of a system clock, and the first refresh instruction and the second refresh instruction are obtained based on division of a refresh instruction.