Bias generation circuit and memory circuit
AssigneeChangxin Memory Technologies, Inc.
InventorZhonglai Liu
Life of this patent
Estimating the term…
Abstract
A bias generation circuit and a memory circuit are provided. The bias generation circuit includes: a first load circuit coupled between a working voltage and an regulating node; a bias circuit configured to receive the working voltage and output a bias voltage according to the working voltage; a voltage stabilizing circuit coupled to an output end of the bias circuit and configured to receive a reference voltage and regulate a voltage of the regulating node according to the bias voltage and the reference voltage; and a second load circuit having one end coupled to the output end of the bias circuit and the other end coupled to the regulating node.
Claims20
A bias generation circuit, comprising:
- a first load circuit coupled between a working voltage and a regulating node;
- a bias circuit configured to receive the working voltage and output a bias voltage according to the working voltage;
- a voltage stabilizing circuit which is coupled to an output end of the bias circuit and configured to receive a reference voltage and regulate a voltage of the regulating node according to the bias voltage and the reference voltage;
- and
- a second load circuit having one end coupled to the output end of the bias circuit and the other end coupled to the regulating node.
A memory circuit, comprising:
- a bias generation circuit, wherein the bias generation circuit comprises:
- a first load circuit coupled between a working voltage and a regulating node;
- a bias circuit configured to receive the working voltage and output a bias voltage according to the working voltage;
- a voltage stabilizing circuit which is coupled to an output end of the bias circuit and configured to receive a reference voltage and regulate a voltage of the regulating node according to the bias voltage and the reference voltage;
- and a second load circuit having one end coupled to the output end of the bias circuit and the other end coupled to the regulating node;
- and
- an input buffer circuit coupled to the output end of the bias circuit.
Dependencies are inferred from the claim text.